发明名称 Semiconductor memory and system apparatus
摘要 A register part of a mode register has a plurality of operation setting parts in which plural types of operating specifications are respectively set to operate the semiconductor memory. The mode register outputs a soft reset signal when at least a value of one-bit of the register part represents a reset state. A reset signal generator outputs a reset signal for resetting an internal circuit in response to the soft reset signal. In the present invention, a system that controls the semiconductor memory is required to necessarily assign a predetermined bit with a setting command of the mode register in order to generate the soft reset signal. Accordingly, it is possible to reliably reset the internal circuit by external control.
申请公布号 US7251171(B2) 申请公布日期 2007.07.31
申请号 US20050167318 申请日期 2005.06.28
申请人 FUJITSU LIMITED. 发明人 NISHIMURA KOICHI;YAMADA SHINICHI;NOMURA YUKIHIRO
分类号 G11C7/00;G11C7/10;G11C8/00 主分类号 G11C7/00
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