发明名称 |
SYSTEM FOR IMPROVING ENDURANCE AND DATA RETENTION IN MEMORY DEVICES |
摘要 |
<p>A memory system includes a memory block having at least one memory cell. The current is sensed after the erase operations of the memory cell. A signal is generated in response to the current dropping below a predetermined level after the erase operations of the memory cell. The stress on the memory cell is reduced to a first reduced level for erase operations occurring subsequent to the current dropping below the predetermined level.</p> |
申请公布号 |
SG133534(A1) |
申请公布日期 |
2007.07.30 |
申请号 |
SG20060087316 |
申请日期 |
2006.12.15 |
申请人 |
CHARTERED SEMICONDUCTOR MANUFACTURING LTD. |
发明人 |
WENBO LI;TAN MAGGIE L.F.;LEE CHWA SIOW;FEI XU |
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