发明名称 CLAMP CIRCUIT AND TEST SIGNAL GENERATOR
摘要 <P>PROBLEM TO BE SOLVED: To solve the problem wherein a clamp voltage is fluctuated due to dynamic resistance to generate a bump on a clamped waveform at a clamp circuit using a Zener diode, and a pulse width is shortened or a feedback loop performance becomes unstable at a clamp circuit of a conventional feedback system due to delay for turning off a surge absorption semiconductor device, thereby, to provide a clamp circuit and a test signal generator capable of generating a flat and accurate load dumping surge test voltage with proper repeatability. <P>SOLUTION: An output of a window comparator with a first reference voltage and a second reference voltage inputted thereinto is adopted as a loop performance reference voltage for a feedback loop circuit. A detected voltage of a load dumping surge waveform is feedback controlled into a voltage width range specified by the two reference voltages, and a flat clamped waveform is acquired. Since the loop performance reference voltage is maintained at substantially constant, loop performance becomes stable at wide range of surge voltage and surge absorption current. <P>COPYRIGHT: (C)2007,JPO&INPIT
申请公布号 JP2007189513(A) 申请公布日期 2007.07.26
申请号 JP20060006060 申请日期 2006.01.13
申请人 KIKUSUI ELECTR0NICS CORP 发明人 NOJIRI MISAO
分类号 H03K5/007;G01R31/00 主分类号 H03K5/007
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