| 摘要 |
A binary phase detecting device ( 2 ) comprises a first decision feedback equaliser (DFE 1 ) connected in parallel with a decision unit (DFE 2 ), which can be devised as a second decision feedback equaliser. Respective outputs (Q) of the first decision feedback equaliser and the decision unit are input to a first ( 8 ) and to a second flip flop ( 9 ), respectively. Using this configuration, the proposed binary phase detecting device overcomes disadvantages of conventional binary phase detectors in the presence of highly distorted input signals, e.g. due to Polarisation Mode Dispersion (PMD), this enabling high-performance clock data recovery (CDR) with increase dispersion tolerance.
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