| 摘要 |
PROBLEM TO BE SOLVED: To provide an interruption processing method capable of eliminating the occurrence of problem by a simple method when an interruption is accepted just after delay in a CPU of a pipeline system which processes an instruction with a delay slot. SOLUTION: The interruption processing method has an instruction decoder 1 which decodes instructions and a flag register 2 which can be set by the instructions in the CPU which performs pipeline processing to a delay instruction with the delay slot and switches the interruption just after the delay instruction to valid or invalid by a state of the flag register 2. COPYRIGHT: (C)2007,JPO&INPIT
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