CMOS devices adapted to reduce latchup and methods of manufacturing the same

摘要

In a first aspect, a first apparatus is provided. The first apparatus is semiconductor device that includes (1) a shallow trench isolation (STI) oxide region; (2) a first metal-oxide-semiconductor field-effect transistor (MOSFET) coupled to a first side of the STI oxide region; (3) a second MOSFET coupled to a second side of the STI oxide region, wherein portions of the first and second MOSFETs form first and second bipolar junction transistors (BJTs) which are coupled into a loop; and (4) a dopant-implanted region below the STI oxide region, wherein the dopant-implanted region forms a portion of the BJT loop and is adapted to reduce a gain of the loop. Numerous other aspects are provided.