发明名称 PARITY GENERATION CIRCUIT, COUNTER AND COUNTING METHOD
摘要 <p>When what values the parity (X&lt;P&gt;) of input data, POP(Z&lt;3:0&gt;), and the parity (Z&lt;P&gt;) of POP will have for 256 values from 0 to 255 that can be provided by 8 bit input data (X&lt;7:0&gt;) is checked, the X&lt;P&gt; and the Z&lt;P&gt; coincide when the POP is any one of "0", "1", "6" and "7", and they are inverted when the POP is any one of "2", "3", "4", "5" and "8". This regularity is utilized for predicting the parity.</p>
申请公布号 WO2007083377(A1) 申请公布日期 2007.07.26
申请号 WO2006JP300749 申请日期 2006.01.19
申请人 FUJITSU LIMITED;YAMASHITA, HIDEO 发明人 YAMASHITA, HIDEO
分类号 H03M13/09;G06F11/10 主分类号 H03M13/09
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