发明名称 STRUCTURE FOR REDUCING OVERLAP CAPACITANCE IN FIELD EFFECT TRANSISTORS
摘要 A field effect transistor (FET) device includes a gate conductor formed over a semiconductor substrate, a source region having a source extension that overlaps and extends under the gate conductor, and a drain region having a drain extension that overlaps and extends under the gate conductor only at selected locations along the width of the gate conductor.
申请公布号 US2007170527(A1) 申请公布日期 2007.07.26
申请号 US20070692453 申请日期 2007.03.28
申请人 INTERNATIONAL BUSINESS MACHINES CORPORATION 发明人 ZHU HUILONG;GLUSCHENKOV OLEG
分类号 H01L29/94 主分类号 H01L29/94
代理机构 代理人
主权项
地址