发明名称 PLANNER STACK PACKAGE
摘要 <p>A planar stack package is provided to prevent the generation of cracks on a chip by lessening a stress due to the difference of shrinkage between the chip and a peripheral portion of the chip using a coating solution. A plurality of chips(120) are spaced apart from each other on a substrate(110). A wire bonding process is performed between the substrate and the plurality of chips. An EMC(Epoxy Molding Compound) is formed on the resultant structure to protect the chip and wires from the outside. The wires are fixed by a coating solution(140), wherein the coating solution is formed on the entire surface of the chip. The coating solution is formed on a portion between the chips.</p>
申请公布号 KR20070077404(A) 申请公布日期 2007.07.26
申请号 KR20060007008 申请日期 2006.01.23
申请人 HYNIX SEMICONDUCTOR INC. 发明人 HYUN, SUNG HO
分类号 H01L23/28 主分类号 H01L23/28
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