| 摘要 |
A semiconductor memory device is provided to perform a cache read operation at a high speed, by judging data of flag cells using a common signal line while data of a second data cache is output to an I/O data line. In a semiconductor memory device, a memory cell array(1) has a plurality of memory cells arranged in a matrix. The memory cell array has a plurality of bit lines connected to the memory cells. N data storage circuits are connected to the bit lines, respectively. Each of the data storing circuits has first and second storage parts storing 1 bit data. A common mutual connection part is connected to the first storage part. A control part reads data from the data storage circuits storing first logic data. Among the N data storage circuits, K data storage circuits store first logic data and (n-k) data storage circuits store second logic data.
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