| 摘要 |
A method for forming bit line patterns in a semiconductor device is provided to prevent a collapse phenomenon by connecting end portions of bit line patterns to each other which are adjacent to an edge of a cell array area. A material layer for a bit line pattern(34) is formed on a semiconductor substrate(31) with a defined cell array area(200). The material layer is patterned to form plural bit line patterns which are spaced apart from each other at a predetermined interval. At least end portions of the bit line patterns are connected to each other. The connected end portions of the bit line patterns are etched to isolate adjacent bit line patterns.
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