发明名称 TWO STEP ARITHMETIC DECODING WITH CONVERSION INTO AN INTERMEDIATE FORMAT
摘要 <p>A decoding-processing apparatus that decodes bitstreams using an intermediate format. The apparatus includes a context-calculating unit (2) calculating the probability of symbols contained in incoming bitstreams, a parameter-generating unit (3) generating parameters for use in the context-calculating unit (2), and an arithmetic decoding-calculating unit (4) decoding the incoming bitstreams in accordance with the probability, thereby providing decoded data. The apparatus also includes a stream-converting unit (5) converting the decoded data into intermediate bitstreams, a storage unit (6) storing the intermediate bitstreams, a synchronization-detecting unit (7) detecting calculation start timing from the intermediate bitstreams fed out of the storage unit (6), thereby providing detected calculation start timing, and a multivalued calculating unit (8) permitting the intermediate bitstreams fed out of the storage unit (6) to be multivalued in synchronism with the detected calculation start timing from the synchronization-detecting unit (7).</p>
申请公布号 EP1810521(A1) 申请公布日期 2007.07.25
申请号 EP20050805939 申请日期 2005.11.02
申请人 MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD. 发明人 TOJIMA, MASAYOSHI;IGUCHI, MASAYASU;ABE, KIYOFUMI;TOIDA, HIROAKI;NISHI, TAKAHIRO
分类号 G06T9/00;H03M7/40;H04N19/00;H04N19/13;H04N19/136;H04N19/157;H04N19/166;H04N19/189;H04N19/40;H04N19/423;H04N19/46;H04N19/65;H04N19/70;H04N19/89;H04N19/91 主分类号 G06T9/00
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