发明名称 Semiconductor device memory cell
摘要 A circuit provides an inhibition to the short circuit between the bit line and the capacitance contact, without employing a self alignment contact (SAC) process. A hard mask is formed on the bit line upper surface and a side wall formed on the side surface of the bit line by etching back a nitride film. A bit contact interlayer film without the SAC structure is etched off except where bit line is formed. A direct nitride film is formed on the entire top and side surface of the bit line so as to cover the bit line in one processing step. Since the upper and side nitride film thicknesses are substantially the same, the height of the bit line can be reduced, enabling further miniaturization. In addition, since the sidewall nitride film is formed without an etch back process, it can more easily be formed with a constant film thickness.
申请公布号 US7247904(B2) 申请公布日期 2007.07.24
申请号 US20060409094 申请日期 2006.04.24
申请人 NEC ELECTRONICS CORPORATION 发明人 INOUE TOMOKO;INOUE KEN
分类号 H01L27/108;H01L21/02;H01L21/768;H01L21/8242;H01L23/522;H01L29/76;H01L29/94;H01L31/119 主分类号 H01L27/108
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