发明名称 |
Clock pulse generator apparatus with reduced jitter clock phase |
摘要 |
Clock pulse generator apparatus comprising a clock pulse generator for generating a train of primary clock pulses having leading and trailing edges. A delay line produces a train of delayed clock pulses presenting delayed edges whose timing relative to corresponding edges of the primary clock pulses is defined by the delay line. A logic circuit produces a train of combined clock pulses presenting leading and trailing edges defined alternately by one of the delayed edges and the corresponding edge of the primary clock pulse, so that the combined clock pulses comprise active clock phases having widths defined by the delay line; the variability of the widths of the active clock phases is smaller than the variability of the positions of the leading and trailing edges of the primary clock pulses.
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申请公布号 |
US2007164884(A1) |
申请公布日期 |
2007.07.19 |
申请号 |
US20040596043 |
申请日期 |
2004.11.26 |
申请人 |
FREESCALE SEMICONDUCTOR, INC. |
发明人 |
IHS HASSAN |
分类号 |
H03M3/00;H03K5/00;H03K5/06;H03K5/13;H03L7/081;H03M3/04 |
主分类号 |
H03M3/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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