| 摘要 |
Systems, methods and circuits for implementing efficient device testing. As one example, a method is disclosed for testing a device that includes both a digital and analog portion. In some cases, the digital portion includes a plurality of latch devices, and the analog portion includes a plurality of memory cells and a plurality of selector devices. Each of the plurality of selector devices is electrically coupled to a respective one of the memory cells, is at least indirectly coupled to one of the plurality of latch, devices, and is controlled by a selector input. In the method, a load clock is applied to the plurality of latch devices such that a pattern is loaded into the plurality of latch devices. The selector input is asserted such that a derivative of the pattern is received by the plurality of selectors and returned to the plurality of latch devices. A system clock is applied to the plurality of latch devices such that the derivative of the pattern is loaded into the plurality of latch devices.
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