| 摘要 |
PROBLEM TO BE SOLVED: To improve address/data communication efficiency in a memory bus. SOLUTION: The memory control device is provided between a processor 30 and memory ranks 40a and 40b, and controls access to the memory ranks 40a and 40b. A memory management unit 10 receives and buffers an access request to the memory ranks 40a and 40b from the processor 30 and issues the access request to a rank management unit 20 based on scheduling in memory management. The rank management unit 20 connects the memory ranks 40a and 40b, receives and buffers the access request from the memory management unit 10, and gives the access request to a predetermined memory rank based on scheduling in rank management. COPYRIGHT: (C)2007,JPO&INPIT
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