发明名称 Data processing system, cache system and method for precisely forming an invalid coherency state indicating a broadcast scope
摘要 A cache coherent data processing system includes at least first and second coherency domains. In a first cache memory within the first coherency domain of the data processing system, a memory block is held in a storage location associated with an address tag and a coherency state field. A determination is made if a home system memory assigned an address associated with the memory block is within the first coherency domain. If not, the coherency state field is set to a coherency state that indicates that the address tag is valid, that the storage location does not contain valid data, the first coherency domain does not contain the home system memory, and that, following formation of the coherency state, the memory block is cached outside of the first coherency domain.
申请公布号 US2007168618(A1) 申请公布日期 2007.07.19
申请号 US20060333615 申请日期 2006.01.17
申请人 CLARK LEO J;GUTHRIE GUY L;STARKE WILLIAM J;STUECHELI JEFFREY A;WILLIAMS DEREK E 发明人 CLARK LEO J.;GUTHRIE GUY L.;STARKE WILLIAM J.;STUECHELI JEFFREY A.;WILLIAMS DEREK E.
分类号 G06F13/28 主分类号 G06F13/28
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