发明名称 PROGRAMMABLE LOGICAL DEVICE
摘要 <p><P>PROBLEM TO BE SOLVED: To provide a programmable logical device capable of decreasing costs and reducing a board area. <P>SOLUTION: A flip-flop 57 stores an output state of a combination logic circuit block (lookup table 56) in an enable state. A multiplexer 58 selects and outputs either the output of the combination logic circuit block or the output of the flip-flop 57. When the output of the flip-flop 57 is selected as an output of the multiplexer 58 in accordance with information included in configuration information, the flip-flop 57 is brought into enable state and when the output of the combination logic circuit is selected, the flip-flop 57 is brought into disable state. Thus, the output state of the combination logic circuit block before configuration switching can be stored and it becomes not necessary to newly provide a memory for storing the result of the former configuration. <P>COPYRIGHT: (C)2007,JPO&INPIT</p>
申请公布号 JP2007184959(A) 申请公布日期 2007.07.19
申请号 JP20070037277 申请日期 2007.02.19
申请人 FUJITSU LTD 发明人 MASUI SHOICHI;OURA MICHIYA;NINOMIYA TSUZUMI;YOKOZEKI WATARU;MUKODA KENJI
分类号 H03K19/177;G11C16/04;H03K3/356;H03K19/185 主分类号 H03K19/177
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