发明名称 |
WAFER LEVEL CHIP SCALE PACKAGE HAVING REROUTING LAYER AND METHOD OF MANUFACTURING THE SAME |
摘要 |
A wafer level chip scale package capable of reducing parasitic capacitances between a rerouting and the metal wiring of a wafer, and a method for manufacturing the same are provided. An embodiment of the wafer level chip scale package includes a wafer arranged with a plurality of bonding pads and an insulating member formed on the wafer so that the bonding pads are exposed. A rerouting is further formed on the insulating member in contact with the exposed bonding pads and an external connecting terminal is electrically connected to a portion of the rerouting. Here, the insulating member overlapping the rerouting is provided with a plurality of spaces in which air is trapped.
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申请公布号 |
US2007164431(A1) |
申请公布日期 |
2007.07.19 |
申请号 |
US20060549933 |
申请日期 |
2006.10.16 |
申请人 |
SAMSUNG ELECTRONICS CO., LTD. |
发明人 |
LEE IN YOUNG;CHUNG HYUN-SOO;LEE DONG-HO;SIM SUNG-MIN;SEO DONG-SOO;RYU SEUNG-KWAN;PARK MYEONG-SOON |
分类号 |
H01L23/48;H01L21/44 |
主分类号 |
H01L23/48 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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