发明名称 CIRCUIT, METHOD, AND APPARATUS FOR BURN-IN TEST AND PATTERN GENERATION PROGRAM
摘要 PROBLEM TO BE SOLVED: To provide an inexpensive burn-in test high in failure detection efficiency. SOLUTION: A burn-in test circuit includes scan chains in which a plurality of scan flip-flops are serially connected to each other; a circuit to be tested to which output signals of any one of the plurality of scan flip-flops are to be input as activation signals; and a loop circuit for scan chains for feeding back and inputting output signals of the scan chains to the scan chains. Signals to be fed back and input to the loop circuit for scan chains are signals according to output of the circuit to be tested. COPYRIGHT: (C)2007,JPO&INPIT
申请公布号 JP2007183130(A) 申请公布日期 2007.07.19
申请号 JP20060000538 申请日期 2006.01.05
申请人 NEC ELECTRONICS CORP 发明人 HARADA EIJI
分类号 G01R31/28;G01R31/26 主分类号 G01R31/28
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