Process sequence and mask layout to reduce junction leakage for a dual gate MOSFET device

摘要

A method of forming a thin gate insulator layer comprises forming an active region surrounded by STI regions; forming a first insulator layer on the active device region; forming a patterned photoresist layer over the first insulator layer and a at least a portion of the STI regions; etching the first insulator layer to expose a portion of the active device region, wherein the photoresist layer substantially protects the STI regions during etching; forming a thin gate insulator layer on the exposed portion of the active device region, wherein said first insulator layer located on a remaining portion of said active device region is converted to a thicker second insulator layer; and forming a conductive gate structure overlying a first portion of the thin gate insulator layer while a second portion of the thin gate insulator layer not covered by the conductive gate structure is removed.