| 摘要 |
A memory circuit and method to reduce array noise due to wordline coupling is disclosed. The circuit includes a plurality of memory cells arranged in rows ( 702, 704 , and 706 ) and columns ( 750, 752 ). Each row has a first part ( 1102 ) and a second part ( 1108 ). A first conductor ( 750 ) is coupled to a respective column of memory cells in each first part. A second conductor ( 752 ) is coupled to a respective column in each second part. A third conductor is coupled to a control terminal of each memory cell in the first part ( 1102 ) of a first row and the second part ( 1108 ) of a second row.
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