| 摘要 |
An embodiment of the invention is a logic minimization method that provides improved user design performance without a substantial increase in user design area. Alternate factorizations are determined for portions of the user design. For each factorization, a delay metric is computed. The user design is optimized by selecting factorizations based on a balance of performance and area considerations. The optimized design is then mapped to the hardware architecture of the programmable device. A first portion of the user design is mapped to maximize performance, while a second portion of the user design is mapped to minimize area. The first portion of the user design includes a set of data paths each having a delay metric above a delay threshold. The delay metric can be derived from a unit delay computation or from timing analysis.
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