ADDRESS DECODER, STORAGE DEVICE, PROCESSOR, AND ADDRESS DECODING METHOD FOR THE STORAGE DEVICE

摘要

PROBLEM TO BE SOLVED: To simplify a circuitry and to reduce power consumption by setting a high processing speed.

SOLUTION: This address decoder includes a plurality of decoding units 13 constituted of combinational logic circuits, an inversion circuit 16 for inverting the outputs of the decoding units 13, and an AND circuit for obtaining a logical product of the output signal of one decoding unit 13 and the output signal of the other decoding unit 13 inverted by the inversion circuit 16.

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