| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To scale down a selective gate transistor for executing selection/non-selection of a plurality of memory cells connected in series. <P>SOLUTION: The device is provided with a memory cell array 11, selection gate transistors SGD, SGS, a control gate driving circuit 12, a selection gate driving circuit 13, and a source line driving circuit 14. The memory cell array 11 has a memory cell array group in which a plurality of memory cells are connected in series. The selection transistor SGD is connected between the end of the memory cell group and a bit line BL. The selection transistor SGS is connected between the other end of the memory cell group and a source line SL, and has a gate length shorter than that of the selection transistor SGD. The control gate driving circuit 12 drives the control gate of the memory cell group, and the selection gate driving circuit 13 drives the gates of the selection transistors SGD and SGS. The source line driving circuit 14 drives the source line SL, and the bit line control circuit 16 provides a bit line potential to the memory cell via the bit line BL. <P>COPYRIGHT: (C)2007,JPO&INPIT</p> |
