| 摘要 |
A method for manufacturing a semiconductor device having a fuse area and a pad area. An inter-layer dielectric layer is deposited over a semiconductor substrate having a metal interconnection. A protection layer is deposited over the inter-layer dielectric layer. A photoresist mask is used to define areas to be etched in the fuse area and a pad area. The protection layer and the inter-layer dielectric layer are etched in the pad area and the fuse area, thereby exposing the metal interconnection in the pad area, and removing the dielectric material to a predetermined depth in a fuse area, using an etching gas including a first component. The first etching process is stopped. A second etching process is performed for selectively etching a surface of the metal interconnection using an etching gas including a second component.
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