发明名称 Parallel processing memory cell
摘要 A digital memory cell incorporated into an integrated circuit in a standard package containing: a two dimensional array of such memory cells each of which can hold one bit of data and each of which incorporates an arithmetic logic unit which can perform logical and arithmetic operations on data bits stored in, or generated by, selected memory cells immediately adjacent to the given cell without need of a sequential clock and; additional support logic to read/write data from/to such memory cells within the array and to program the arithmetic logic unit in each such memory cell to perform a desired function.
申请公布号 US2007162710(A1) 申请公布日期 2007.07.12
申请号 US20060475266 申请日期 2006.06.26
申请人 WISEMAN VICTOR A 发明人 WISEMAN VICTOR A.
分类号 G06F13/00 主分类号 G06F13/00
代理机构 代理人
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