发明名称 PERFORMING DIRECT CACHE ACCESS TRANSACTIONS BASED ON A MEMORY ACCESS DATA STRUCTURE
摘要 Embodiments of an apparatus, method, and system for encoding direct cache access transactions based on a memory access data structure are disclosed. In one embodiment, an apparatus includes memory access logic and transaction logic. The memory access logic is to determine whether to allow a memory access based on a memory access data structure. The transaction logic is to assign direct cache access attributes to a transaction based on the memory access data structure.
申请公布号 WO2007078958(A2) 申请公布日期 2007.07.12
申请号 WO2006US48555 申请日期 2006.12.18
申请人 INTEL CORPORATION;MADUKKARUMUKUMANA, RAJESH, SANKARAN;MUTHRASANALLUR, SRIDHAR;HUGGAHALLI, RAMAKRISHNA;ILLIKKAL, RAMESHKUMAR 发明人 MADUKKARUMUKUMANA, RAJESH, SANKARAN;MUTHRASANALLUR, SRIDHAR;HUGGAHALLI, RAMAKRISHNA;ILLIKKAL, RAMESHKUMAR
分类号 G06F12/10;G06F12/08;G06F12/14 主分类号 G06F12/10
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