| 摘要 |
A method for forming metal silicide layers in a high-k/metal gate transistor comprises forming a transistor with a sacrificial gate on a substrate, depositing a first ILD layer on the substrate, removing the sacrificial gate to form a gate trench, depositing a high-ft: dielectric layer within the gate trench, annealing the high-k dielectric layer, depositing a first metal layer within the gate trench, depositing a second ILD layer on the first ILD layer and the transistor, etching the first and second ILD layers to form a first contact trench and a second contact trench that extend down to a source region and a drain region of the transistor, depositing a second metal layer within the contact trenches, annealing the second metal layer to form metal silicide layers, and depositing a third metal layer within the first and second contact trenches to fill the contact trenches. |
