发明名称 |
PER-SET RELAXATION OF CACHE INCLUSION |
摘要 |
A multi-core processor includes a plurality of processors and a shared cache. Cache control logic implements an inclusive cache scheme among the shared cache and the local caches for the processors. Counters are maintained to track instances, per set, when a processor chooses to delay eviction from the local cache. While the counter indicates that one or more delayed evictions are pending for a set, the cache control logic treats the set as non-inclusive, broadcasting foreign snoops to all of the local caches, regardless of whether the snoop hits in the shared cache. Other embodiments are also described and claimed. |
申请公布号 |
WO2007078647(A2) |
申请公布日期 |
2007.07.12 |
申请号 |
WO2006US47140 |
申请日期 |
2006.12.06 |
申请人 |
INTEL CORPORATION;RAJWAR, RAVI;MATTINA, MATTHEW |
发明人 |
RAJWAR, RAVI;MATTINA, MATTHEW |
分类号 |
G06F12/08 |
主分类号 |
G06F12/08 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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