| 摘要 |
Control data is efficiently serially transferred to a motor drive device (12) for driving a motor without involving the CPU. Specific memory addresses are allocated to data buffers (BF1 - BFn). An address decoder (42) decodes a memory address output to an address bus (30) and applies a write enable signal to the corresponding data buffer to write data to the data buffer by DMA transfer. When data is written to any data buffer, a sequencer circuit (44) stores control data compiled based on data in data buffers BF1 - BFn in a shift register 46, and serially transfers the control data to a serial transfer line (20) synchronized to a clock. <IMAGE> |
