发明名称 Method and apparatus for voltage compensation for parasitic impedance
摘要 An apparatus and method for regulating a voltage to a load to compensate for one or more parasitic impedances. A first amplifier measures the voltage drop due to a first parasitic impedance, and a second amplifier measures the voltage drop due to a second parasitic impedance. An offset generator sums the first and second voltage drops with a reference voltage, and drives a DC-to-DC converter to produce an input voltage matching the summed voltages. Accordingly, the voltage at a load between the parasitic impedances matches the reference voltage. The load may be, for example, a computer microprocessor or central processing unit.
申请公布号 US7242169(B2) 申请公布日期 2007.07.10
申请号 US20050069362 申请日期 2005.03.01
申请人 APPLE INC. 发明人 KANAMORI TAKASHI;KIM STEPHEN J.;JAUREGUI DAVID
分类号 G05F1/00 主分类号 G05F1/00
代理机构 代理人
主权项
地址