发明名称 Architecture for switching packets in a high-speed switching environment
摘要 A system for switching packets in a high-speed switching environment includes one or more memory structures, multiple input structures that can each write to each of the one or more memory structures, and a first switching structure that couples the input structures to the one or more memory structures. The system also includes multiple output structures that can each read from each of the one or more memory structures and communicate a first portion of a packet to a first component of a communications network before an input structure has received a second portion of the packet from a second component of the communications network. The system also includes a second switching structure that couples the plurality of output structures to the one or more memory structures. The second switching structure is coupled to the one or more memory structures by a first number of links and coupled to the plurality of output structures by a second number of links, and the first number of links is twice or more the second number of links.
申请公布号 US7242684(B2) 申请公布日期 2007.07.10
申请号 US20030360094 申请日期 2003.02.07
申请人 FUJITSU LIMITED 发明人 NAKAGAWA YUKIHIRO;SHIMIZU TAKESHI
分类号 H04B3/20;H04L12/56 主分类号 H04B3/20
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