发明名称 |
Method and apparatus for generating parity information for error correction |
摘要 |
A method of generating error correction parity information using a parity check matrix having m rows and n columns, wherein m is a number of parity bits and n is a number of codeword bits, wherein a same fixed number of elements in each of the rows has a value of 1 and all remaining elements in each of the rows has a value of 0, and wherein a same fixed number of elements in each of the columns has a value of 1 and all remaining elements in each of the columns has a value of 0, the error correction method including generating a lower triangular matrix in 1st through k-th rows and (n-m+1)-th through (n-m+k)-th columns of the parity check matrix by performing row and column permutations on the parity check matrix, wherein k<m; and obtaining m parity bits using the parity check matrix including the lower triangular matrix and (n-m) message bits.
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申请公布号 |
US7243286(B2) |
申请公布日期 |
2007.07.10 |
申请号 |
US20030738203 |
申请日期 |
2003.12.18 |
申请人 |
SAMSUNG ELECTRONICS CO., LTD. |
发明人 |
KIM KI-HYUN;HAN SUNG-HYU;PARK IN-SIK;SHIM JAE-SEONG;LEE YOON-WOO |
分类号 |
G06F11/10;H03M13/13;H03M13/11;H03M13/19 |
主分类号 |
G06F11/10 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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