| 摘要 |
A microprocessor capable of reducing bus traffic and a method thereof are provided to prevent power consumption by enabling a chip bus to be operated in a low frequency without increasing a compression ratio of image data. A bus(110) transfers the image data between each IP(Intellectual Property) in the microprocessor(100). A repeat signal generator(120a or 120b) generates a repeat signal by counting the number continuously repeating the same image data as the unit image data. The unit image data is the data scanned in one scanning cycle. The microprocessor reduces the bus traffic by scanning the unit image data as many as the repeat number in response to the repeat signal. The IP is a memory controller(130) controlling read/write of the image data to an external memory(200), an accelerator(150), and a display controller(140) receiving and scanning the image data to an external display panel(300). The display controller includes a scanning controller by scanning the unit image data as many as the repeat number in the response to the repeat signal.
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