| 摘要 |
Complex control procedures using direct memory access by a first DMA processing unit 54 sending control data to a first control unit by means of DMA channels 54-1 to 54-n, and a second DMA processing unit 56 sending control data to a second controller 36 by means of DMA channels 56-1 to 56-m. The first DMA processing unit 54 also has a branching controller 52 as a DMA channel for transferring timing data to a second timer 40. When a time specified by the received timing data passes, the second timer 40 sends an activation signal to DMA channel 56-1 of the second DMA processing unit 56, and the DMA channels 56-1 to 56-m are thereafter sequentially activated. |
