| 摘要 |
A phased-locked loop phase detector for digital input signals in which digital summed value for a particular number of bits is equal to zero. Sampled and digitized data comprising a delay stage for delaying the data signal by a one or more sampling clock period is supplied to the phase detector as an input signal. The delayed data signal and the undelayed data signal are then supplied to a subtraction stage. The difference between the two input values is formed in this subtraction stage. The processing stage assigns one of a plurality of possible values to the respective differential value. The full differential value range is subdivided in a number of sub-ranges corresponding to the plurality of possible values. All differential values in one sub-range are assigned the same output value. The output of the subtraction stage is supplied to a filter/control stage.
|
