| 摘要 |
An integrated circuit device includes a processing component and a cache, which is arranged to store data for use by the processing component responsively to an addressing scheme based on memory addresses having an address length of ml bits. First and second buses are coupled between the processing component and the cache, the buses having bus widths of n<SUB>1 </SUB>and n<SUB>2 </SUB>bits, respectively, such that n<SUB>1</SUB><M<SUB>1</SUB>. The processing component and the cache each include a respective address bus expander coupled to the first bus in order to compact at least some of the memory addresses for transmission over the first bus so that each of the at least some memory addresses is transmitted over the first bus in one cycle of the first bus.
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