| 摘要 |
A counter circuit of a semiconductor memory device is provided to prevent clock skew and jitter phenomenon due to high frequency usage, by operating each counter part using a delay clock having narrower clock width than an external clock. A delay clock generation part(140) receives an external clock and generates a number of delay clocks with a narrower clock width than the external clock. A first counter part(110) receives the external clock and outputs a first counting clock and a first carry combined signal by using a number of unit counters. A second counter part(120) receives one delay clock and the first carry combined signal and outputs a second counting clock and a second carry combined signal. A third counter part(130) receives one delay clock and the second carry combined signal and outputs a third counting clock and a third carry combined signal.
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