| 摘要 |
A data output predriver of a semiconductor memory device is provided to increase timing margin of a rising clock signal and a falling clock signal by generating a rising clock signal synchronized to rising latch data and a falling clock signal synchronized to falling latch data during data output of the semiconductor memory device. A delay part(546) outputs a rising clock delay signal and a falling clock delay signal by delaying a rising clock signal and a falling clock signal provided from a DLL(Delay Locked Loop) circuit part. A rising data input part(542) receives and transfers rising latch data latched by the rising clock signal to a common node. A falling data input part(544) receives and transfers falling latch data latched by the falling clock signal at an enable time of the falling clock signal to the common node. A falling output data generation part generates falling output data synchronously with a rising edge time of the rising clock signal by receiving the falling data, and then provides the falling output data to the falling data input part.
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