发明名称 |
Via structure and process for forming the same |
摘要 |
Via structure and process flow for interconnection in a semiconductor product. A bottom metal layer is provided to represent a connection layer in the semiconductor product. An isolation layer on the bottom metal layer comprises a via hole exposing a portion of the bottom metal layer. The via hole comprises a sidewall and a bottom. A first barrier metal layer is disposed on the sidewall of the via hole, but not on the bottom of the via hole. A metal under-layer is formed on the bottom of the via hole and on the first barrier metal layer. A second barrier metal layer is formed on the metal under-layer. A metal fill layer fills the via hole. A lattice mismatch between the metal under-layer and the second barrier metal layer is less than about 5%.
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申请公布号 |
US2007152342(A1) |
申请公布日期 |
2007.07.05 |
申请号 |
US20050323484 |
申请日期 |
2005.12.30 |
申请人 |
TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD. |
发明人 |
TSAO JUNG-CHIH;CHEN KEI-WEI;LU YING-JING;WANG YU-SHENG;LIN YU-KU |
分类号 |
H01L23/52 |
主分类号 |
H01L23/52 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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