| 摘要 |
Provided is a method for forming a semiconductor wafer having an insulator. According to the method, an insulating layer pattern and a silicon germanium layer are formed on a wafer, and a structure similar to a SOI wafer is formed. Accordingly, since the thin insulating layer pattern exists between the surface of the wafer, in which a circuit is formed, and a lower layer thereof, parasitic capacitance is reduced and thus device performance can be improved. In addition, punch through due to a short channel effect, DIBL and leakage current can be solved as with the SOI wafer. Further, the insulating layer pattern is formed instead of an insulating layer formed on the SOI wafer, so that holes are prevented from being stacked in a neutral region. Consequently, a floating body effect can be prevented from occurring.
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