发明名称 ARRAY CIRCUIT SUBSTRATE AND WIRE BONDING PROCESS USING THE SAME
摘要 An array circuit substrate including a plurality of substrate units, a plurality of non-stick test circuits, and a plurality of etching windows is provided. Each of the substrate units has a plurality of wire-bond pads and a plurality of plated wires. One of the plated wires is connected to one of the corresponding wire-bond pads, and at least one of the plated wires is a test wire. The non-stick test circuits are respectively disposed between two adjacent substrate units. Each test wire is connected to a test point through the non-stick test circuits. The etching windows are located on the substrate units. The plated wires are respectively cut by the etching windows except the test wires. Furthermore, the non-stick test circuits are not cut by the etching windows.
申请公布号 US2007152348(A1) 申请公布日期 2007.07.05
申请号 US20060309680 申请日期 2006.09.11
申请人 发明人 CHEN YING-CHIH;TIEN YUN-HSIANG
分类号 H01L23/48 主分类号 H01L23/48
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