| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To provide an FFT arithmetic circuit capable of coping with a plurality of FFT lengths without providing a plurality of arithmetic circuits corresponding to the number of equipment, as in the prior art, capable of reducing the number of circuits and capable of reducing electric power consumption. <P>SOLUTION: This FFT arithmetic circuit of the present invention is an FFT arithmetic unit comprising a plurality of butterfly computing parts connected in series, and capable of selecting optionally the FFT length of a computation object to be set, and the butterfly computing part is provided with a temporary storage part for storing once input signals, and has a signal sequence converting part for reading out sequentially the signals, according to an order of conducting complex multiplication and complex subtraction in butterfly computation, a coefficient storage part stored with a complex coefficient complex-multiplied to the each signal, corresponding to the FFT length, a complex multiplication part for reading out sequentially the corresponding complex coefficient from the complex coefficient storage part, in the every read-out signal, and a complex multiplication and subtraction part for complex-multiplying and complex-subtracting sequentially the signals output from the complex multiplication part and complex-multiplied with the complex coefficient. <P>COPYRIGHT: (C)2007,JPO&INPIT</p> |
