| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To cope with an increase in the number of pad electrodes or fine pitch without damaging semiconductor IC chips built in a resin layer by heat or application of load (stress). <P>SOLUTION: First, copper foils 12 provided on both surfaces of a core substrate 11 are selectively removed by photolithography and etching, thus forming a conductive pattern 13 such as wiring or land, on the core substrate 11. Next, a semiconductor IC chip 14 is mounted face-up in a specified area on the core substrate 11, and then it is buried in a resin sheet 16. A copper foil 17 formed on the surface of the resin sheet 16 is selectively removed by conformal treatment, thus forming a mask pattern for forming a via hole. Then, the copper foil 17 applied with the conformal treatment is used as a mask, and sand-blasting is conducted to form a via hole 19. <P>COPYRIGHT: (C)2007,JPO&INPIT</p> |
