| 摘要 |
PROBLEM TO BE SOLVED: To provide a WDT circuit capable of attaining operating frequency improvement and stabilization. SOLUTION: An input buffer 2 converts input clocks into a positive-phase clock and a negative-phase clock, and a peak hold circuit 11 delays the positive-phase clock. A variable capacitive element 3 determines a delay amount thereof. A NAND circuit 4 performs NAND operation between the negative-phase clock and an output of the peak hold circuit, and a means value detection circuit 9 detects a mean value of outputs of the NAND circuit. A control circuit 10 performs control so that an electrostatic capacitance value of the variable capacitive element increases as the detected mean value decreases. Two stages of flip-flops 6, 7 perform toggle operations with a clock from a timer oscillator 5 which outputs a clock of the almost identical frequency as the clock, as an input and are reset with the output of the NAND circuit. COPYRIGHT: (C)2007,JPO&INPIT
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