| 摘要 |
A full-adder module (30) comprises a full-adder comprising a plurality of input and output terminals, a sum generation unit and a carry generation unit. The carry generation unit comprises a programmable inverter arranged to selectively invert a carry-in bit to the carry generating unit in response to a control signal applied to one of the input terminals. The full-adder module (30) provides an area-efficient logic block that supports signed multiplications, the logic block retaining its programmable nature and being capable of performing all the other operations it was intended to perform. |
