发明名称 POWER SOURCE MONITORING CIRCUIT
摘要 PROBLEM TO BE SOLVED: To avoid various problems in an inside of a semiconductor integrated circuit such as a system LSI, even when deficient power source supply and an unstable operation occur in one system out of two lines of power sources comprising a high source voltage system and a low source voltage system. SOLUTION: The integrated circuit includes a peripheral circuit I/O and Per_Cir with the first source voltage VDD1 supplied from the first power source circuit VDD1_Reg, and an inside core Core_Cir with the second source voltage VDD2 supplied from the second power source circuit VDD2_Reg. A voltage detecting circuit Volt_Det of this power source monitoring circuit Spvs_IC of the present invention detects that a level of the the first source voltage VDD1 goes down to an operation prohibition range of the peripheral circuit I/O and Per_Cir, even when a level of the second source voltage VDD2 is within an operation allowance range of the inside core Core_Cir. A control output signal VDDSup_CNT from a control circuit Cntrlr of the power source monitoring Spvs_IC lowers a supply voltage level VDD2_Sup to a circuit block of the second source voltage VDD2 from the second power source circuit VDD2_Reg. COPYRIGHT: (C)2007,JPO&INPIT
申请公布号 JP2007171133(A) 申请公布日期 2007.07.05
申请号 JP20050373033 申请日期 2005.12.26
申请人 RENESAS TECHNOLOGY CORP 发明人 TAKANASHI TOSHIHIKO;NAGAI DAIICHI
分类号 G01R19/165 主分类号 G01R19/165
代理机构 代理人
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