发明名称 TEST PATTERN GENERATION SYSTEM AND METHOD
摘要 PROBLEM TO BE SOLVED: To generate a test pattern capable of testing an LSI efficiently. SOLUTION: This method for generating a test pattern 14 used for a test of the LSI including a single via SV and a redundant via RV, has (A) a step for extracting a single via structure SV distinctively from a redundant via structure RV by referring to layout data 12, (B) a step for counting the number of single via structures SV to each of a plurality of nets included in the LSI by referring to a net list 11, and (C) a step for generating the test pattern 14 for testing preferentially a net having more single via structures SV among the plurality of nets. COPYRIGHT: (C)2007,JPO&INPIT
申请公布号 JP2007171084(A) 申请公布日期 2007.07.05
申请号 JP20050371621 申请日期 2005.12.26
申请人 NEC ELECTRONICS CORP 发明人 HIRABAYASHI KYOSUKE
分类号 G01R31/3183;G06F17/50;H01L21/82 主分类号 G01R31/3183
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