发明名称 |
FREQUENCY MODULATED OUTPUT CLOCK FROM A DIGITAL FREQUENCY/PHASE LOCKED LOOP |
摘要 |
A frequency modulated output of a Digital Locked Loop (DLL) is implemented with a Johnson Counter outputting a sample clock and a synchronized digital code at a multiple of the sample clock. The digital code drives a digital-to-analog converter to generate a frequency modulated control signal. The control signal is summed with the center frequency control from the digital locked loop digital filter to provide a frequency modulated center frequency control signal to the DLL oscillator.
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申请公布号 |
US2007152766(A1) |
申请公布日期 |
2007.07.05 |
申请号 |
US20060557721 |
申请日期 |
2006.11.08 |
申请人 |
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发明人 |
HERRIN SCOTT W;DAO CHRIS C.;FALVEY PATRICK M.;RODRIGUEZ THOMAS J.;CAMPBELL JULES D. |
分类号 |
H03L7/085 |
主分类号 |
H03L7/085 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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